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NXP Semiconductors /LPC5410x /GPIO /MASK0

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Interpret as MASK0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MASKP

Description

Mask register port 0/1

Fields

MASKP

Controls which bits corresponding to PIOm_n are active in the MPORT register. Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data